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1 for more information www.linear.com/lt3095 typical application features description dual-channel low noise bias generators the lt ? 3095 generates two low noise bias supplies from a common input voltage ranging from 3v to 20v. each channel includes a fixed frequency, peak current-mode step-up switching regulator and a low noise, single- resistor-programmable 50ma linear regulator. the linear regulators high power supply ripple rejection (psrr) combined with its low noise performance results in less than 100v p-p output ripple and noise. each boost regulator adjusts its output voltage to 2v above the corresponding linear regulators output voltage, opti - mizing power dissipation, psrr and transient response. this tracking scheme, along with internal boost regulator frequency compensation and integrated schottky diodes, minimizes external component count and simplifies system design. each linear regulator includes internal current limit and thermal limit protection circuitry. the lt3095 switching frequency is externally program - mable with a single resistor from 450khz to 2mhz. a sync pin allows synchronization to an external clock . the lt3095 is available in a thermally enhanced, low profile (0.75mm) 24-lead 3mm??5mm qfn package. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. output ripple applications n generates two independent low noise bias supplies n boost regulator: n wide input voltage range: 3v to 20v n adjustable switching frequency : 450khz to 2mhz n synchronizable to external clock n 950ma power switches n integrated schottky diodes n internal frequency compensation n linear regulator: n wide output voltage range: 1v to 20v n set pin reference current: 50a n low noise: 4v rms (10hz to 100khz) n high frequency psrr: 72db at 1mhz n independent precision-threshold enable pins n symmetric pinout simplifies pcb layout n thermally enhanced 3mm 5mm 24-lead qfn package n noise-sensitive usb powered applications n data conversion, industrial supplies, rf n instrumentation amplifiers 3095 ta01a lt3095 3095fa 300k 10f 2.2f 1f 0.1f en1 sw1 gnd bstout1 ldoin1 6.8h out1 set1 rt gnd in en2 sw2 gnd bstout2 ldoin2 2.2f out2 set2 intv cc gnd v in 3v to 7v lt3095 v out1 5v, 50ma v out2 15v, 50ma sync 100k 1s/div v bstout 20mv/div v out 50v/div 3095 g03 v in = 5v v out = 15v i load = 50ma f osc = 1mhz 10f 20mhz bw 2.2f 1f 100k 10h
2 for more information www.linear.com/lt3095 pin configuration absolute maximum ratings in , set1 , set2 ........................................................ 24 v sw1 , sw2, ................................................................ 24 v out1 , out2 ................................................... 24 v , C0. 3v e n1 , e n2 .. ..................................................... 24v , C 0. 3v ldoi n1 , ldoi n2 , bstout1 , bstout2 ..................... 24v rt, sync .................................................................... 6v o perating junction temperature ( note 2 ) e- grade , i-grade ................................ C 40 c to 125c mp- grade .......................................... C 55 c to 125c storage temperature range .................. C 65 c to 150c (note 1) 24 23 22 21 9 10 top view 25 gnd udd package 24-lead (3mm 5mm) plastic qfn 11 12 6 5 4 3 2 1 15 16 17 18 19 20 gnd bstout1 nc intv cc gnd ldoin1 gnd out1 gnd bstout2 sync rt gnd ldoin2 gnd out2 14 7 13 8 sw1 in in sw2 set1 en1 en2 set2 t jmax = 125c, ja = 38c/w, jc = 5.0c/w exposed pad (pin 25) is gnd, must be soldered to pcb order information electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 5v, sync?=?0v unless otherwise noted. lead free finish tape and reel part marking package description temperature range lt3095eudd#pbf lt3095eudd#trpbf lgrq 24-lead (3mm x 5mm) plastic qfn C40c to 125c lt3095iudd#pbf lt3095iudd#trpbf lgrq 24-lead (3mm x 5mm) plastic qfn C40c to 125c lt3095mpudd#pbf lt3095mpudd#trpbf lgrq 24-lead (3mm x 5mm) plastic qfn C55c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. symbol parameter conditions min typ max units v in input voltage supply range l 3 20 v i in v in pin supply current v en1 ?=?v en2 ?=?5.0v, v in ?=?5v (not switching) 3.25 5 ma v en1 ?=?v en2 ?=?0.3v, v in ?=?20v (shutdown) 1.6 5 a v en1,2 v trip (off to on) v en1,2 rising l 1.12 1.23 1.35 v enable threshold hysteresis 110 125 135 mv enable pin current v en ?=?5v 1 5 a (http://www .linear.com/product/lt3095#orderinfo) lt3095 3095fa
3 for more information www.linear.com/lt3095 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the lt3095e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. the lt3095i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3095mp is 100% tested over the C55c to 125c operating junction temperature range. symbol parameter conditions min typ max units intv cc intv cc voltage v en1 ?=?v en2 ?=?5v 2.7 v intv cc under voltage lockout v en1 ?=?v en2 ?=?5v, intv cc rising l 2.25 2.4 2.55 v intv cc under voltage lockout hysteresis v en1 ?=?v en2 ?=?5v 300 mv boost regulator boost (v ldoin C v out ) differential regulation voltage v en1 ?=?v en2 ?=?5v, v out ?=?10v, i load ?=?0ma l 1.85 2 2.15 v boost maximum duty cycle f osc ?=?1mhz l 90 % switch pin leakage current switch off, v sw ?=?12v 0.01 1 a boost switch peak current limit (note 3) l 0.8 0.95 1.1 a switch v cesat i sw ?=?400ma 250 mv osc oscillator frequency rt?=?210k, v in ?=?5v rt?=?100k, v in ?=?5v rt?=?44.5k, v in ?=?5v l l l 0.47 0.95 1.85 0 .5 1 2 0.53 1.05 2.15 mhz mhz mhz sync duty cycle range v sync ?=?0v to 1.5v pulse 20 80 % sync pin input current v sync ?=?5v 15 20 a sync threshold f osc ?=?1mhz, 50% duty cycle l 0.8 1.1 1.3 v ldo linear regulator ldo set pin current v out ?=?10v, i load ?=?0ma 49.5 50 50.5 a v out ?=?1v to 20v, i load ?=?0ma to 50ma l 49 50 51 a offset voltage (v out C v set ) v out ?=?10v, i load ?=?0ma C1 0.15 1 mv ldo voltage regulation: i set ldo voltage regulation: v os (note 5) v out ?=?3v to 20v, i load ?=?0ma v out ?=?1v to 20v, i load ?=?0ma C60 C50 C100 na v ldo load regulation: i set ldo load regulation: v os (note 4) v out ?=?10v, i load ?=?0ma to 50ma v out ?=?10v, i load ?=?0ma to 50ma 100 C6 150 na mv ldoin supply current i load ?=?0ma 450 a ripple rejection 3v < v out < 20v, i load ?=?50ma f ripple ?=?450khz, c set ?=?0.1f, c out ?=?2.2f, i load ?=?50ma f ripple ?=?1mhz, c set ?=?0.1f, c out ?=?2.2f, i load ?=?50ma f ripple ?=?2mhz, c set ?=?0.1f, c out ?=?2.2f, i load ?=?50ma 73 72 71 db ldo output noise voltage v out ?=?5v, i load ?=?50ma, c set ?=?0.47f, c out ?=?2.2f, bw?=?10hz to 100khz. 4 v rms ldo output current limit v out ?=?1v to 20v l 55 70 ma note 3: the boost peak current limit is measured in a low frequency test mode. in operation at high frequencies, the inductor current may exceed this value due to delays in the control circuitry. note 4: linear technology ? is unable to guarantee maximum load regulation due to production test limitations with kelvin-sensing the package pins. please consult the typical performance characteristics for curves of output regulation as a function of load current. note 5: for v out ??1.25v. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = 5v, sync?=?0v unless otherwise noted. lt3095 3095fa
4 for more information www.linear.com/lt3095 typical performance characteristics efficiency transient output ripple transient output ripple linear regulator transient response set pin current set pin current distribution set pin current set pin current offset voltage (v out ?C?v set ) t a = 25c, unless otherwise noted. v in = 5v v out = 15v i load = 50ma f osc = 1mhz 350mhz bw v in = 5v v out1 = 5v v out2 = 15v c out = 2.2f ch1 load step = 1ma to 50ma lt3095 3095fa 12 1s/div v bstout 20mv/div v out 50v/div 3095 g03 v in = 5v v out = 15v i load = 50ma f osc = 1mhz 14 20mhz bw 5s/div i out 50ma/div v out1 10mv/div v out2 10mv/div 3095 g04 v out = 10v 16 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 18 150 49.0 49.2 49.4 49.6 49.8 50.0 50.2 50.4 50.6 20 50.8 51.0 set pin current (a) 3095 g05 n = 10298 i set distribution (a) 49 49.5 50 50.5 49.0 51 3095 g06 49.2 49.4 49.6 50.0 v in = 5v 50.2 50.4 50.6 49.8 50.8 51.0 set pin current (a) 3095 g07 output current (ma) 0 set pin voltage (v) 10 20 30 40 50 set pin current (a) 3095 g08 49.0 49.2 49.4 0 49.6 50.0 50.2 50.4 50.6 49.8 50.8 51.0 v out = 10v i load = 0ma 2 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 4 150 0 50 100 150 200 250 300 offset voltage (v) 3095 g09 6 f sw = 1mhz v out1 = 5v v out2 = 15v i load1 = i load2 v in = 5v v in = 3.3v load current (ma) 0 10 20 8 30 40 50 0 10 20 30 40 50 60 10 70 80 efficiency (%) 3095 g01 1s/div v bstout 20mv/div v out 5mv/div 3095 g02
5 for more information www.linear.com/lt3095 typical performance characteristics offset voltage (v out ?C?v set ) offset voltage distribution offset voltage (v out ?C?v set ) ldo current limit ldo current limit en turn-on threshold en pin hysteresis en pin current en pin current t a = 25c, unless otherwise noted. lt3095 3095fa 12 75 100 125 1.20 1.21 1.22 1.23 1.24 turn?on threshold (v) 3095 g15 14 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125 16 100 110 120 130 140 150 en pin hysteresis (mv) 3095 g16 v en = v in = 5v temperature (c) 18 ?75 ?50 ?25 0 25 50 75 100 125 150 20 0.4 0.6 0.8 1.0 1.2 1.4 en pin current (a) 3095 g17 v in = 5v en pin voltage (v) 0 0 2 4 6 8 10 12 14 16 18 20 20 0 1 2 3 4 5 en pin current (a) 3095 g18 40 60 80 i load = 1ma 100 offset voltage (v) 3095 g10 n = 10298 v os distribution (mv) ?1 ?0.5 0 0.5 1 output voltage (v) 3095 g11 ?40c 25c 125c output current (ma) 0 10 20 30 40 0 50 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 2 1 offset voltage (mv) 3095 g12 temperature (c) ?75 ?50 ?25 0 25 50 4 75 100 125 150 55 60 65 70 75 80 6 ldo current limit (ma) 3095 g13 v out = v set ? 200mv output voltage (v) 0 2 4 6 8 10 8 12 14 16 18 20 60.0 65.0 70.0 75.0 80.0 10 ldo current limit (ma) 3095 g14 v in = 5v temperature (c) ?75 ?50 ?25 0 25 50
6 for more information www.linear.com/lt3095 typical performance characteristics differential voltage (v ldoin ?C?v out ) boost tracking ldo differential (v ldoin ?C?v out ) boost switch peak current limit boost switch peak current limit switch drop power schottky i-v characteristic switching frequency switching frequency t a = 25c, unless otherwise noted. lt3095 3095fa 0 ?25 0 25 50 75 100 125 150 800 850 25 900 950 1000 1050 1100 switch current limit (ma) 3095 g23 v in = 5v switch current (ma) 0 50 250 500 750 1000 0 100 200 300 400 500 75 switch drop (mv) 3095 g24 forward voltage (v) 0.4 0.6 0.8 1.0 1.2 0 0.1 100 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 schottky current (a) 125 3095 g25 rt (k) 0 50 100 150 200 250 200 400 150 600 800 1000 1200 1400 1600 1800 2000 2200 frequency (khz) 1.85 3095 g26 rt = 100k temperature (c) ?75 ?50 ?25 0 25 50 75 1.90 100 125 150 950 960 970 980 990 1000 1010 1.95 1020 1030 1040 1050 frequency (khz) 3095 g27 v in = 5v 2.00 2.05 2.10 2.15 v ldoin - v out (v) lt3095 g19 v in = 3v i load = 1ma v ldoin ? v out v ldoin = v bstout v out = 12v v out (v) 0 2 4 6 8 10 12 14 16 i load = 0ma 18 20 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 i load = 50ma 2.20 0 3 6 9 12 15 18 21 24 temperature (c) v ldoin ? v out (v) boost output voltage (v) 3095 g20 output current (ma) 0 10 20 30 40 50 ?75 1.85 1.90 1.95 2.00 2.05 2.10 2.15 ldo differential (v) 3095 g21 v in = 5v ?50 duty cycle (%) 0 20 40 60 80 100 800 850 900 ?25 950 1000 1050 1100 switch current limit (ma) 3095 g22 v in = 5v temperature (c) ?75 ?50
7 for more information www.linear.com/lt3095 typical performance characteristics switching frequency switching frequency maximum duty cycle sync threshold sync pin current quiescent current in shutdown (both channels, boost + ldo) quiescent current in shutdown (both channels, boost + ldo) quiescent current boost transient response t a = 25c, unless otherwise noted. lt3095 3095fa 75 150 13.0 13.5 14.0 14.5 15.0 15.5 16.0 sync pin current (a) 3095 g32 100 v en1 = v en2 = 0v v in = 5v v in = 20v temperature (c) ?75 ?50 ?25 0 25 50 125 75 100 125 150 0 25 50 75 100 125 150 150 175 200 quiescent current (a) 3095 g33 v en1 = v en2 = 0v input voltage (v) 0 2 4 470 6 8 10 12 14 16 18 20 0 1.0 480 2.0 3.0 4.0 5.0 quiescent current (a) 3095 g34 v in = 5v v en1 = v en2 = 5v v in pin v ldoin pin temperature (c) 490 ?75 ?50 ?25 0 25 50 75 100 125 150 500 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 510 5.0 quiescent current (ma) 3095 g35 v in = 5v v out = 12v 100s/div i load 50ma/div v bst 100mv/div 520 3095 g36 rt = 210k 530 frequency (khz) 3095 g28 rt = 44.5k temperature (c) ?75 ?50 ?25 0 25 temperature (c) 50 75 100 125 150 1.85 1.90 1.95 2.00 2.05 ?75 2.10 2.15 frequency (mhz) 3095 g29 v out = 20v i load = 20ma oscillator frequency (mhz) 0.4 0.6 0.8 ?50 1 1.2 1.4 1.6 1.8 2.0 90 92 94 96 ?25 98 100 maximum duty cycle (%) 3095 g30 v in = 5v temperature (c) ?75 ?50 ?25 0 0 25 50 75 100 125 150 0.75 0.80 0.85 0.90 25 0.95 1.00 1.05 1.10 1.15 1.20 1.25 sync threshold (v) 3095 g31 v sync = v in = 5v 50 temperature (c) ?75 ?50 ?25 0 25 50 75 100 125
8 for more information www.linear.com/lt3095 typical performance characteristics start up response sync acquisition integrated rms thermal noise (10hz C 100khz) noise spectral density noise spectral density noise spectral density linear regulator power supply rejection ratio linear regulator power supply rejection ratio linear regulator power supply rejection ratio t a = 25c, unless otherwise noted. lt3095 3095fa 10v/div frequency (hz) 10 100 1k 10k 100k 1m 10m 0.1 1 i l 10 100 1k 10k output noise (nv/hz) 3095 g42 v ldoin = 7v v out = 5v c out = 2.2f i load = 50ma 500ma/div c set = 10nf c set = 100nf c set = 1f frequency (hz) 10 100 1k 10k 100k 1m v intvcc 10m 20 30 40 50 60 70 80 90 100 5v/div 110 120 psrr (db) 3095 g43 v ldoin = 7v v out = 5v c set = 0.1f i load = 50ma c out = 2.2f c out = 4.7f 3095 g37 c out = 10f frequency (hz) 10 100 1k 10k 100k 1m 10m 20 rt = 100k 30 40 50 60 70 80 90 100 110 120 f sync = 1.5mhz psrr (db) 3095 g44 v ldoin = 7v v out = 5v c out = 2.2f c set = 0.1f i load = 50ma i load = 20ma i load = 10ma i load = 1ma 1s/div frequency (hz) 10 100 1k 10k 100k 1m 10m 20 30 v sync 40 50 60 70 80 90 100 110 120 psrr (db) r set1 = 240k 2v/div 3095 g45 v sw2 20v/div v sw1 10v/div 3095 g38 c out = 2.2f i out = 50ma r set = 100k r set = 240k c set1 = 10nf set pin capacitance (f) 0.01 0.1 1 0 5 10 15 20 25 1ms/div 30 35 40 45 rms output noise (v rms ) 3095 g39 v ldoin = 7v v out = 5v c out = 2.2f i out = 50ma v en1 c set = 0.01f c set = 0.1f c set = 1f frequency (hz) 10 100 1k 10k 100k 1m 5v/div 10m 0.1 1 10 100 1k 10k output noise (nv/hz) 3095 g40 v ldoin = 7v v bstout1 v out = 5v c set = 0.1f i out = 50ma c out = 2.2f c out = 4.7f c out = 10f frequency (hz) 10 100 1k 10v/div 10k 100k 1m 10m 0.1 1 10 100 1k 10k v out1 output noise (nv/hz) 3095 g41 v ldoin = 7v v out = 5v c out = 2.2f c set = 0.1f i out = 50ma i out = 20ma i out = 10ma i out = 1ma
9 for more information www.linear.com/lt3095 pin functions gnd ( pins 1, 5, 7, 14, 16, 20, exposed pad pin 25): ground. tie the exposed pad pin 25 directly to all other gnd pins for optimum performance . the exposed pad provides enhanced thermal performance with its connec - tion to the pcb ground. bstout1 ( pin 2 ): channel 1 step-up regulator output. this pin is channel 1s boost converter output. connect bstout1 directly to ldoin1. connect the boost output capacitor directly from bstout1 to pin 1 s gnd. an internal feedback loop regulates bstout1s voltage typically to (out1 + 2v). this optimizes transient response and psrr performance of the linear regulator. nc ( pin 3): no connect. pin 3 has no internal electrical connection and may be floated or tied to gnd. intv cc ( pin 4): internal regulator output. intv cc powers most of the internal circuitry for both channels . it nomi - nally regulates to 2.7v. intv cc is not designed to power any external load and should not be driven. connect a minimum value 0.1f or higher ceramic capacitor directly from intv cc to pin 5s gnd. ldoin1 ( pin 6): channel 1 linear regulator input. this pin is channel 1 s linear regulator input supply pin. connect pin 6 directly to bstout1 at pin 2. out1 ( pin 8): channel 1 linear regulator output. this pin supplies power to channel 1 s load. use a minimum value 2.2f ceramic capacitor with an esr less than 0.1 to prevent oscillations. large load transient applications require larger value output capacitors to limit peak volt - age transients. see the applications information section for more information on output capacitance . connect the output capacitor and the load directly to pin 7s gnd. set1 ( pin 9): output voltage set. this pin is the non- inverting input to channel 1s ldo error amplifier and the regulation setpoint. a precision, trimmed 50 a flows out of set1. connecting a resistor from set1 to gnd programs channel 1s output voltage (v out = 50a ? r set1 , ohms law). output voltage ranges from 1v to 20v. connecting a capacitor from set1 to pin 7s gnd improves transient response, psrr, noise performance and soft starts the output. set1 requires a minimum capacitor of 10nf. larger value capacitors reduce output noise while correspond - ingly increasing startup time. for precision applications, an external reference or power supply may drive set1 (see applications information section ). this power supply must be current-limited to < 1ma or diode-clamped to exceed v ldoin1 by no more than 1v. e n1 ( pin 10): channel 1 s enable. pulling en1 low disables channel 1s boost converter and linear regulator, thus turning the output off. its typical rising threshold is 1.23v with 125mv of hysteresis. pulling both en1 and en2 low activates the micropower shutdown state in which internal circuit blocks shared by both channels are also disabled . en1 can be used as a digital shutdown pin or, with the use of an external resistor divider, an external v in uvlo threshold can be programmed. if en1 is unused, tie en1 to v in . do not float en1. en2 (pin 11): channel 2s enable. pulling en2 low turns off channel 2s boost converter and linear regulator, thus turning the output off. its typical rising threshold is 1.23v with 125mv of hysteresis. pulling both en1 and en2 low activates the micropower shutdown state in which internal circuit blocks shared by both channels are also disabled . en2 can be used as a shutdown pin or, with the use of an external resistor divider, an external v in uvlo threshold can be programmed . if en2 is unused, tie en2 to v in . do not float en2. set2 ( pin 12): output voltage set. this pin is the non- inverting input to channel 2s ldo error amplifier and the regulation setpoint. a precision, trimmed 50 a flows out of set2. connecting a resistor from set2 to gnd programs channel 2 s output voltage (v out2 = 50a ? r set2 , ohms law). output voltage ranges from 1v to 20v. connecting a capacitor from set2 to pin 14s gnd improves transient response, psrr, noise performance and soft starts the output. set2 requires a minimum capacitor of 10nf. larger value capacitors reduce output noise while correspond - ingly increasing startup time. for precision applications, an external reference or power supply may drive set2 (see applications information section ). this power supply must be current-limited to < 1ma or diode-clamped to exceed v ldoin2 by no more than 1v. lt3095 3095fa
10 for more information www.linear.com/lt3095 pin functions out2 ( pin 13): channel 2 linear regulator output. this pin supplies power to channel 2 s load. use a minimum value 2.2f ceramic capacitor with an esr less than 0.1 to prevent oscillations. large load transient applications require larger value output capacitors to limit peak volt - age transients. see the applications information section for more information on output capacitance . return the output capacitor and the load directly to pin 14s gnd. ldoin2 ( pin 15): channel 2 linear regulator input. this pin is channel 2s linear regulator input supply pin. con - nect pin 15 directly to bstout2 at pin 19. rt ( pin 17): oscillator frequency target. a single resistor from rt to ground programs the internal oscillator from 450khz to 2mhz. if synchronizing to an external clock, connect a resistor to program the oscillator to a frequency close to the sync clock frequency. do not load the rt pin with a capacitor. sync ( pin 18): external clock synchronization input. ground this pin to use the internal oscillator . tie to a logic-level clock source for external synchronization . do not leave floating. bstout2 ( pin 19): channel 2 step-up regulator output. this pin is channel 2s boost converter output. connect bstout2 directly to ldoin2. connect the boost output capacitor directly from bstout2 to pin 20s gnd. an internal feedback loop regulates bstout2s voltage typi - cally to (out2 + 2v). this optimizes transient response and psrr performance of the linear regulator. sw2 (21): channel 2 step-up regulator switch node. the sw pin is connected internally to the collector of the power switch and schottky anode of the corresponding boost regulator. this is the path for boost input power of channel 2. in ( pins 23, 22): input bias supply. the in pins supply current to the intv cc regulator and switch drivers. these pins must be locally bypassed with a minimum of 2.2f of low-esr capacitance. place the positive terminal of the capacitor as close as possible to in pins and return near to pin 1 & pin 20s gnd. note that pins 22 and 23 are internally connected. sw1 (24): channel 1 step-up regulator switch node. the sw pin is connected internally to the collector of the power switch and schottky anode of the corresponding boost regulator. this is the path for boost input power of channel 1. lt3095 3095fa
11 for more information www.linear.com/lt3095 block diagram + ? + ? 3095 bd ? + ? + + ? + ? + ? + ? + ? + ? + ? + ? + ? + ? + ? in lt3095 3095fa 1.23v 1 2 6 8 9 10 7 5 16 50a 11 2v 50a 21 22 20 19 15 13 12 1.23v 14 2v boost current control intv cc clk1 en1 uvlob 1x bandgap 24 oscillator en1 uvlob in sw1 gnd bstout1 ldoin1 set1 out1 23 gnd en1 intv cc rt sync gnd gnd intv cc intv cc boost current 4 control intv cc clk2 en2 uvlob 1x en2 uvlob in sw2 17 gnd bstout2 ldoin2 set2 out2 gnd intv cc uvlob en2 en1 18 en2 clk1 clk2 2.4v
12 for more information www.linear.com/lt3095 applications information the lt3095 is an easy-to-use step-up bias generator with two independent channels supporting loads up to 50ma. since the boost converters are monolithic and feature in - ternal compensation, the lt3095 is easy to configure with a few external components . the output of each switcher is post-regulated by a linear regulator to filter output ripple and provide a precision dc voltage with very low noise for biasing sensitive circuits and sensors . the output of each channel is programmed with a single resistor and internal feedback automatically regulates the output of each boost converter to 2v above the corresponding linear regulators output. the filtered outputs are protected by independent current limit and thermal shutdown. 3095 f01 + ? + ? + ? + ? v in sw1 bstout1 ldoin1 gnd set1 out1 2v 10f 2.2f 50a r set1 ctrl v in l 1 figure?1. lt3095 architecture (single channel) programming the output voltage figure? 1 illustrates the architecture of the lt3095. the boost converter simply regulates the difference between ldoin and out C no external feedback configuration is necessary. the linear regulators have a single-resistor- programmable reference architecture . an accurate, temperature-compensated 50a current flows out of the set pin and into an external resistor, r set , to establish the reference for the linear regulator output voltage . to program the output, simply choose the appropriate set pin resistor according to ohms law: r set = v out 50a the set pin voltage is buffered to the output, so the linear regulator always operates in unity gain configuration. this allows optimal loop gain and bandwidth regardless of output voltage. with this architecture, it is also possible to drive the set pin externally for a dynamic supply (see the typical applications section below). the lt3095 step-up regulator tracks the output of the linear regulator and maintains 2v typically between ldoin and out of each channel. this input-to-output voltage control obviates the need to externally program the boost output voltage and insures controlled power dissipation in the linear regulator pass device, even if the target output voltage is adjusted or programmed dynamically during operation. boost output capacitor / linear regulator input capacitor the lt3095 step-up converters are internally compensated and require an output capacitor, which also serves as the input capacitor for the linear regulator. a value of 10f is recommended. consider capacitance degradation under bias and temperature conditions, as outlined below. the connection of the boost output capacitor on the pcb is crucial for ripple performance , as discussed in the pin functions section. linear regulator stability & output capacitor the lt3095 linear regulators are stable with a minimum output capacitance of 2.2f (esr < 0.1). use low-esr multilayer ceramic capacitors and give consideration to the actual capacitance under bias and temperature condi - tions. see the effective operating capacitance section for more information. th e linear regulator feedback loop has very high bandwidth , allowing it to respond quickly to load steps and actively correct input ripple feed-through up to frequencies near the self-resonance of a typical multilayer ceramic capaci - lt3095 3095fa
13 for more information www.linear.com/lt3095 tor. as an example, the loop bandwidth driving a 50ma load with c out = 2.2f is about 1mhz. with such a high bandwidth, the parasitic series resistance and inductance of the output capacitor can have a noticeable impact on the loop dynamics near the unity gain frequency. if the phase response of the loop is degraded, transient output ringing can result and supply ripple rejection may suffer . avoid these problems by using ceramic capacitors with esr less than 100m; place the capacitor as close as possible to the out pin and return directly to the adjacent gnd pin. see the discussion of board layout below for an example pcb design that meets these requirements. if capacitor types with higher esr (>100 m) or lower self-resonant frequencies (< 500 khz) must be used, it may be necessary to parallel several output capacitors . this lowers the effective esr and esl and can have beneficial effects on ripple rejection. using an output capacitor with a value greater than the minimum 2.2f can improve ripple rejection under certain conditions, as shown in the typical performance plots. however, due to limitations in parasitic electromagnetic coupling, the advantages may not be dramatic in practice. a value of 2.2f is recommended for most applications. set pin (reference bypass) capacitance within the bandwidth of the linear regulator, wideband thermal noise and injected ripple at the output of the lt3095 s built-in reference ( that is, the set pin) are replicated at the output. minimize this source of noise by using an external capacitor to bypass the set pin. table ? 1 shows the total rms output noise in a 10hz to 100khz bandwidth and a 1khz to 20mhz bandwidth for several different values of c set in a typical application. the lower-bandwidth measurement reflects thermal and shot noise only, while the higher-bandwidth measurement includes residual ripple components from the switch - ing converter. both are influenced by the value of c set . a minimum of 10nf is required, but noise is reduced substantially with c set 100nf. applications information table?1. output noise for different values of c set cset v out-ac (v rms 10hz to 100khz) v out-ac (v rms 1khz to 20mhz) 10nf 35 40 47nf 15 25 100nf 12 25 470nf 7 25 1f 4 25 single channel operation, v in = 5v, v out = 18v, i load = 50ma, c out = 2.2f, c bstout = 10f a system level consideration that may limit the value of c set is start-up time: when the part is enabled from shutdown, the set pin voltage rises with a time constant of r set ? c set . since out tracks set, this causes the linear regulator output to soft-start. if very fast startup is required and noise performance cannot be compromised , use an auxiliary circuit to speed up the start time or drive the set pin externally (see typical applications). effective operating capacitance the effective capacitance of a multilayer ceramic capacitor varies over temperature and dc bias conditions, and may be considerably lower than the manufacturers nominal value. to ensure stable operation of the lt3095, make sure that the boost and linear regulator output capacitors meet the minimum requirement in their actual operating conditions, after accounting for temperature and dc bias. 3095 f02 figure?2. capacitance degradation with dc bias voltage lt3095 3095fa 15 20 0 2 4 6 8 10 12 effective capacitance (f) all capacitors x5r, 25v rating 0805 1206 1210 dc bias voltage (v) 0 5 10
14 for more information www.linear.com/lt3095 applications information capacitance degradation under dc bias can be dramatic . in some cases, the effective value of a capacitor may be less than 20% of the nominal value, even at voltages well below the nominal voltage rating of the component. dif - ferent dielectric materials have different sensitivities to dc bias , with x5r and x7r offering good performance . package size also has a large influence on the effective capacitance achieved at higher voltages. in general, capaci - tors in physically larger packages suffer less degradation under dc bias than capacitors of the same voltage rating in a smaller size . figure? 2 shows typical bias curves for three x5r capacitors with nominal values of 10f, all rated for 25v, but in different package sizes. the effective values of some ceramic capacitors can also degrade significantly with temperature , as figure ?3 demonstrates . of the common dielectric types , x5r and x7r offer relatively stable capacitance over a wide tem - perature range . b oth are widely available in a variety of sizes and values. temperature (c) ?50 ?100 change in value (%) ?80 250?25 50 75 100 3095 f03 0 20 40 ?60 ?40 y5v ?20 125 both capacitors are 16v, 1210 case size, 10f x5r figure?3. capacitance de-rating with temperature in the case of the linear regulator output capacitor, the regulator can show ringing or degraded ripple rejection if the effective capacitance is more than 20 % below the recommended minimum of 2.2f. the recommended minimum value for c bstout the output capacitor for the boost converter is 10f; however, lower effective values may be tolerable in certain applications. at high duty cycles, for example, the linearized transconductance of the current control loop is reduced, and less output capacitance is required to achieve the same unity gain frequency. when using a boost output capacitor with ef - fective capacitance below 8f, verify the loop dynamics experimentally or with an ac model to ensure adequate loop stability in realistic operating conditions . programming the switching frequency the lt3095 s two switching regulator channels run out of phase to reduce input current ripple amplitude . an internal oscillator generates a precise clock that can be programmed from 450khz to 2mhz by connecting an external resistor from the rt pin to ground . table? 2 lists the closest 1% resistor values for a few common frequencies. refer to the typical performance section for a plot of clock frequency as a function of rt. table?2. sw frequency vs rt value f osc (mhz) rt (k) 0.45 232 0.50 210 0.75 137 1.00 100 1.50 63.4 2.00 44.2 alternatively, an external frequency source can be used to synchronize the switching edges to a system clock using the sync pin. the voltage and duty-cycle requirements for the logic level sync signal are listed in the electrical characteristics table. when using the sync pin to set the frequency, connect a resistor to the rt pin as if program - ming the oscillator to the sync frequency. use a resistor with 1% tolerance to insure appropriate scaling of internal control signals. the lt3095 will sense a pulsed signal on the sync pin and override the oscillator to align the switch edges with the external clock. when using the internal oscillator, each channel will run at the programmed switching frequency , f osc , and the power switches will turn on 180o out-of-phase. if sync functionality is used, each channel will run at the sync pulse frequency : one power switch will turn on at the ris - ing edge of the sync input, and the other power switch at the falling edge . lt3095 3095fa
15 for more information www.linear.com/lt3095 inductor selection & boost loop stability the choice of inductor for the boost converter affects the system efficiency, loop stability, and solution size. as a starting point , choose a value which results in 30 % current ripple when the switcher is operating at its peak current of about 1a. the minimum inductor value that satisfies this requirement can be calculated from the input and output voltages and the switching frequency: l min = v in ? 0.5 ( ) v out + 3 ? v in ( ) 0.3 v out + 3 ( ) f sw where v out is the programmed voltage at the output of the linear regulator, and v in is the supply of the inductor current. in some cases, it may be appealing to use a smaller inductor value because of solution size or other constrains. before reducing the inductance, there are some considerations that must be taken into account. a smaller inductor will result in increased output ripple and additional conduc - tion losses in the inductor and power switch. higher peak currents will translate to increased emi radiation during switching , which can easily couple frequency content onto the output of the linear regulators. furthermore, a small inductor may make the current-control loop unstable in continuous conduction mode, causing subharmonic oscillations in the inductor current. this can introduce unpredictable spectral content into the system. subharmonic oscillation is only a concern for duty cycles greater than 50%, and can be avoided by making sure the inductor meets the following requirement: l > v out ? v in + 3 1.25v 1h for d < 0.75 l > v out ? v in + 3 2.50v 1h for d > 0.75 where d = 1? v in ? 0.5 v out + 3 applications information finally, with a low inductance, the converter may operate at or near discontinuous conduction mode, even at large loads. while stability is guaranteed in discontinuous conduction mode, switch node ringing may introduce new frequency components into the system. in extreme cases (e.g. high boost ratio and heavy load), the step-up converter may not be able to deliver 50ma average output current, even when the inductor is energized to the switch peak current limit each clock cycle. use an inductor with a sufficient current rating to prevent core saturation, which can cause the effective inductance to drop dramatically and the current to jump very quickly . in case of runaway, an internal protection circuit senses very high currents in the internal catch diode and prevents the power switch from turning on until the inductor current falls. this safety mechanism protects the power switch, but damage to the power schottky diode or overvoltage of the boost converters output are still possible. for these reasons, avoid inductor core saturation during normal operation: choose an inductor rated for the peak current in your application, with appropriate margin for tolerances and transient overshoot. if in doubt, a rating of 1.5a will provide insurance against saturation in all normal operat - ing conditions. regarding switching supply loop stability , it is well known that the control loop of a boost converter has an inherent right half-plane zero. fundamentally, this is due to the fact that current is not delivered to the load while the inductor is being energized . thus, when the loop commands more current, the output voltage temporarily drops. a linearized approximation of the zero frequency is: f zero,rhp = v bst 1? d ( ) 2 2 li load where v bst is the output of the boost converter (ap- proximately v out + 3v), d is the switch duty cycle, and l is the inductor value. when this zero falls near the loop unity gain frequency (typically around 50khz), phase margin is degraded. for this reason, avoid inductor values much larger than suggested by the 30% ripple calculation given above. lt3095 3095fa
16 for more information www.linear.com/lt3095 applications information high frequency edges & passive filtering techniques figure? 4 shows the output of the lt3095 boost converter in a typical application with a 50ma load, before and after filtering by the linear regulator. the most noticeable residual switching feature is the short spike when the boost power switch turns off . this edge is generated by high di/ dt cir - culating through the boost output capacitor parasitic and the corresponding magnetic circuit on the pcb. these edges can couple onto the output of the linear regulator indirectly through parasitic capacitance in the linear regulator or electromagnetically from one pcb trace to another . the spikes contain high frequency (>1mhz) content that the linear regulator control loop cannot ac - tively filter out. minimize the residual spike amplitude by following the pcb layout guidelines provided in the next section . in many applications, the energy associated with the residual spikes is at a sufficiently high frequency that it does not interfere with the load. figure?4. output transient showing spikes in cases where extreme ripple rejection up to very high frequencies is required , a passive filter at the output of the ldo can be used . form a pi-network by placing the output capacitor very close to the lt3095 and another capacitor directly at the load , as shown figure ?5. make sure the additional capacitor is large enough to present low impedance to the load across the full frequency range . pcb trace inductance between the lt3095 and load will provide some high-frequency filtering , but passives with additional impedance can offer further improvement . one option is a small resistor typically an ohm or less to avoid introducing a large load regulation term to the voltage seen at the load . another option is a low-esr chip ferrite- bead or inductor . this solution offers the best rejection at very high frequencies (> 10 mhz ); however , a resonance is formed at a frequency of 1/ 2 l filter c load ( ) that can amplify noise and introduce a new ripple component at the load . the peaking , or q , associated with the filter can be reduced by introducing a series damping resistor or reducing the ratio l filter /c load . 3095 f05 figure?5. pi network filter figure 6 shows the residual noise at the output of the ldo after it has been filtered with a 0.1 resistor and an additional 1f capacitor at the load . the high frequency switch edges have been substantially reduced. figure?6. residual ripple with passive pi filter lt3095 3095fa v bstout 20mv/div v out 50v/div 3095 f04 c out 2.2f 0.1 c load 1f gnd out1 data0 lt3095 load data0 data0 v in = 5v v out = 15v i load = 50ma f osc = 1mhz 20mhz bw 1s/div data1 v bstout 20mv/div v out 50v/div 3095 f06 v in = 5v v out = 15v i load = 50ma f osc = 1mhz 20mhz bw 1s/div
17 for more information www.linear.com/lt3095 board layout figure? 7 shows a compact two-layer pcb layout designed to minimize the residual switching content at the output. perhaps the most important component placement is the boost output capacitor , c bstout . a high frequency hot loop is formed by the internal power switch, the schottky diode, and c bstout . the inductance of this loop generates spikes in the boost output and radiates high frequency electromagnetic energy that can feed through the parasitic capacitance of the linear regulator or couple directly to the post-regulator output. minimize the size of the loop applications information by placing the output capacitor as close as possible to the bstout and adjacent gnd pins. do not force current to flow through vias while circulating around this loop . furthermore, minimize the sw node trace area to prevent electrostatic coupling of the high dv/dt signal. while the boost converter hot loop generates electromag - netic energy, the ldo output and reference traces act as antennas that can pick up and deliver it to the load. reduce coupling onto the output by minimizing the unshielded output pcb trace area and returning c out and c set as close as possible to the adjacent gnd pin. also take care 3095 f07 c bst0ut1 c bst0ut2 c out1 c out2 l1 l2 figure?7. example pcb layout, top layer (demo board dc2270a) lt3095 3095fa
18 for more information www.linear.com/lt3095 applications information to eliminate any ground loops between this return point and the reference ground of the regulators load. in a multilayer board, shielding the output trace with ground conductors can also help prevent coupling. the presence of a solid ground plane underneath the routing traces can significantly reduce electromagnetic radiation and coupling. the dielectric thickness separat - ing the signal traces and ground plane determine how effective it is . for more information on this topic, and an extended discussion of pcb layout for high-frequency switching converters , read application note 139 C power supply layout and emi. the same principles that apply to emi generation by stand-alone switching converters apply to lt3095 applications where residual ripple is of critical concern. in the end, electromagnetic coupling is likely to be responsible for most of the frequency content observed at the lt3095 output. thermal considerations the lt3095 has an internal thermal limiting circuit that will protect the device under overload conditions . for continuous normal load conditions , do not exceed the 125 c maximum junction temperature . care - fully consider all sources of thermal resistance from ju nction-to-ambient . this includes ( but is not limited to ) junction-to-case , case-to-heat sink interface , heat sink resistance or circuit board-to-ambient , as the application dictates. consider all additional , adjacent heat generating sources in proximity on the pcb . surface mount packages provide the necessary heat sinking by using the heat spreading capabilities of the pc board, copper traces and planes. surface mount heat sinks, plated through-holes and solder-filled vias can also spread the heat generated by power devices. junction-to-case thermal resistance is specified from the ic junction to the bottom of the case directly, or the bot - tom of the pin most directly in the heat path. this is the lowest thermal resistance path for heat flow . only proper device mounting ensures the best possible thermal flow from this area of the packages to the heat sinking material. for further information on thermal resistance and using thermal information, refer to jedec standard jesd51, notably jesd51-12. in typical applications, where v in is below the desired output voltage , the boost converter will maintain 2v across the linear regulator pass device. in this case, the power dissipation in the linear regulators will be limited to a few hundred milliwatts, even at full load. in applications where the input voltage may exceed one or both of the outputs, the linear regulator will dissipate approximately (v in ?C? v out )???i load . in this case, power dissipation may be substantial and extra care should be taken to ensure the maximum junction temperature is not exceeded. lt3095 3095fa
19 for more information www.linear.com/lt3095 typical applications 5v v in with 5v and 15v outputs and v in uvlo = 4v 3095 ta03 l1: coilcraft lps4012-682mrb l2: coilcraft lps4012-103mrb 5v to 20v v in with 5v and 12v outputs and sepic on channel 2 for continuous output current 3095 ta03 l2 15h l1 = coilcraft lps4012-222mr l2 = wrth 74489430150t d1 = on semi mbr130 v f = internal boost regulator schottky forward voltage d1 float lt3095 3095fa v out1 5v, 50ma v out2 15v, 50ma l1 6.8h 2.2f 10f l2 10h 10f 113k 1% 50k 1% en1 100k 1% sw1 gnd bstout1 ldoin1 out1 set1 rt gnd in en2 2.2f sw2 gnd bstout2 ldoin2 out2 set2 intv cc gnd v in 5v 10% 0.1f lt3095 sync l1 2.2h 2.2f 100k 1% 10f 2.2f 0.1f 100k 243k 1% 100k 1f 2.2f 0.1f 0.1f 15h 10f en1 sw1 gnd bstout1 300k 1% ldoin1 out1 set1 rt gnd v in en2 sw2 gnd bstout2 2.2f ldoin2 out2 set2 intv cc gnd v in 5v to 20v lt3095 v out1 5v, 50ma v out2 12v, 50ma 0.1f sync ldoin = v in ? v f when v in > v out ? 3v, ldo regulates out 0.1f
20 for more information www.linear.com/lt3095 package description please refer to http://www .linear.com/product/ltc3095#packaging for the most recent package drawings. 3.00 0.10 1.50 ref 5.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 23 24 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or 0.25 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (udd24) qfn 0808 rev ? recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 3.50 ref 4.10 0.05 5.50 0.05 1.50 ref 2.10 0.05 3.50 0.05 package outline r = 0.05 typ 1.65 0.10 3.65 0.10 1.65 0.05 udd package 24-lead plastic qfn (3mm 5mm) (reference ltc dwg # 05-08-1833 rev ?) 3.65 0.05 0.50 bsc lt3095 3095fa
21 for more information www.linear.com/lt3095 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . revision history rev date description page number a 03/16 changed title of graph changed bandwidth in set pin section modified high frequency edges section 1 13 16 lt3095 3095fa
22 for more information www.linear.com/lt3095 ? linear technology corporation 2015 lt 0316 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com/lt3095 related parts typical application part number description comments lt3048 low noise bias generator in 2mm 2mm dfn v in : 2.7v to 4.8v, 40ma ldo, 300ma boost switch, noise: <120v rms (10hz to 100khz), 2mm 2mm dfn package lt3042 20v, 200ma, ultralow noise, ultrahigh psrr rf linear regulator v in : 1.8v to 20v, noise: 0.8v rms (10hz to 100khz), psrr: 79db at 1mhz, dfn and mse packages LT3080 1 .1a, parallelable, low noise, low dropout linear regulator v in : 1.2v to 36v, low noise: 40v rms , v out : 0v to 35.7v, current-based reference with 1-resistor v out set; to-220, dd-pak, sot-223, msop and 3mm 3mm dfn-8 packages lt c3260 low noise dual supply inverting charge pump v in : 4.5v to 32v, inverting charge pump generates Cv in , positive and negative ldo with 50ma max, 3mm 4mm dfn and msop packages 3095 ta04 dac l1: vishay ihlp-2525czer100m51 l2: vishay ihlp-2525czer150m51 programmable outputs with tracking lt3095 3095fa 10f 2.2f 0.1f 0.1f en1 sw1 gnd bstout1 ldoin1 out1 v dac set1 rt gnd in en2 sw2 gnd bstout2 ldoin2 out2 l1 10h set2 intv cc gnd v in 5v lt3095 v out1 = v dac , 50ma v out2 = v dac + 2v, 50ma sync 2.2f 10f 2.2f 100k l2 15h 40k

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